1. Field of the Invention
The present invention relates generally to a method of filling high aspect ratio vias and lines in very-large-scale-integrated (VLSI) metal interconnection structures, and more particularly, to depositing a low melting point alloy of a low resistivity metal into the high aspect ratio vias and lines and then purifying the alloy in place to leave the low resistivity metal in the structure.
2. Description of the Prior Art
The problem of filling high aspect ratio vias (height-to-diameter ratio which exceeds unity) and lines (height-to-width ratio which exceeds unity) in VLSI interconnection structures is usually an extremely difficult one. The problem is increased when the vias and lines have vertical or near-vertical walls in addition to high aspect ratios. For high performance VLSI devices, high conductivity metal interconnections must be formed in high aspect ratio vias and line structures, at submicrometer dimensions. The deposition methods must also operate below 400.degree. C. in order to be compatible with polymer interlevel dielectrics.
Traditional physical vapor deposition (PVD) methods, including sputtering and evaporation, exhibit poor step coverage which limits their ability to fill structures with aspect ratios greater than one. Metal chemical vapor deposition (CVD) is an alternative filling method, but has only been successfully developed for a few specific metals, such as tungsten, in the temperature range below 400.degree. C. Selective electroless plating disclosed in U.S. Pat. No. 4,692,349 has also been successfully used to fill high aspect ratio vias in VLSI devices but has only been developed for cobalt and nickel in the temperature range below 400.degree. C. The final result of the plating technique is a high aspect ratio via filled with a cobalt or nickel alloy without any purification of the deposited alloys. U.S. Pat. No. 4,673,592 discloses a method for filling high aspect ratio vias with intermetallic compounds using multiple steps of deposition and laser assisted removal of excess material from low thermal conductivity areas, such as silicon dioxide. However, high temperatures are required for the removal steps and no purification is disclosed. None of the above-mentioned methods have been successfully developed for gold, silver or copper.
It is well established that sputter deposition at a high fraction of the melting point of a metal is a successful method for filling high aspect ratio vias and lines and even allows planarization during the deposition process. For example, an alloy of Al.sub.0.96 Cu.sub.0.04, which has a melting point of 640.degree. C. has been successfully deposited at a temperature of 500.degree. C. However, 500.degree. C. is too high for polymer interlevel dielectrics and furthermore, the Al-4% Cu metallurgy has a much higher resistivity than a pure metal such as gold, silver or copper.
Current efforts for the deposition of copper into high aspect ratio vias and lines in VLSI interconnection structures are focused on the deposition of pure copper directly into the interconnection structure but these efforts have not as of yet been commercially successful. Thus, there is a need to develop a low temperature method for filling high aspect ratio vias and lines with a low resistivity metal such as gold, silver or copper.